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| rev.1.10 jul 15, 2007 page 1 of 65 m32c/8a group renesas mcu rej03b0213-0110 rev.1.10 jul 15, 2007 1. overview 1.1 features the m32c/8a group is a single-chip control mcu, fa bricated using high-performance silicon gate cmos technology, embedding the m32c/80 series cpu core. the m32c/8a group is housed in 144-pin and 100-pin plastic molded lqfp packages. with a 16-mbyte address space, this mcu combines adva nced instruction manipulatio n capabilities to process complex instructions by less bytes and execute instructions at higher speed. the m32c/8a group has a multiplier and dmac adequa te for office automation, communication devices and industrial equipment, and other high-speed processing applications. 1.1.1 applications audio, cameras, office/communica tion/portable eq uipment, etc. 1.1.2 specifications tables 1.11.3 to 1.4 lists the specifications of the m32c/8a group. the m32c/8a group is romless device. use the m32c/8a group in microprocessor mode after reset.
m32c/8a group rev.1.10 jul 15, 2007 page 2 of 65 table 1.1 specifications (144-pin version) (1) item function specification cpu central processing unit m32c/80 core (multiplier: 16 bits 16 bits 32 bits, multiply-addition operation instructions: 16 16 + 48 48 bits) ? basic instructions: 108 ? minimum instruction execution time: 31.3 ns ( f(cpu) = 32 mhz / vcc1 = 4.2 to 5.5 v) 41.7 ns ( f(cpu) = 24 mhz / vcc1 = 3.0 to 5.5 v) ? operating mode: microprocessor mode memory rom, ram see table 1.5 product list . power supply voltage detection vdet3 detection functi on, vdet4 detection function, cold start/warm start determination function external bus expansion bus / memory expansion function ? address space: 16 mbyte ? external bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 v and 5 v interfaces ? bus format: switchable between separate and multiplexed bus formats, switchable data bu s width (8-bit or 16-bit) clock clock generation circuits ? 4 circuits: main clock, sub clock, on-chip oscillator, pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop detectio n function ? frequency divider circuit: dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 ? low power consumption features: wait mode, stop mode interrupts ? interrupt vectors: 70 ? external interrupt inputs: nmi 1 int 3 (16-bit external bus width) int 6 (8- bit external bus width) key input 4 ? interrupt priority levels: 7 watchdog timer 15-bit 1 (with prescaler) dma dmac ? 4 channels, cycle steal method ? trigger sources: 31 ? transfer modes: 2 (single transfer and repeat transfer) dmac ii ? can be activated by all peripheral function interrupt sources ? transfer modes: 2 (single transfer and burst transfer) ? immediate transfer, calculation transfer, and chain transfer functions timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse width modulation (pwm) mode) event counter 2-phase pulse signal processing (2-phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode timer function for 3-phase motor control 3-phase inverter control 1 (using timer a1, timer a2, timer a4, and timer b2) on-chip dead time timer m32c/8a group rev.1.10 jul 15, 2007 page 3 of 65 table 1.2 specifications (144-pin version) (2) notes: 1. iebus is a registered trademark of nec electronics corporation. 2. please contact a renesas sales office to use the optional feature. item function specification serial interface uart0 to uart4 clock synchr onous / asynchronous 5 i 2 c bus (optional) (2) , special mode 2, gci mode, sim mode iebus (optional) (1)(2) a/d converter 10-bit resolution x 18 channels, includes sample and hold function d/a converter 8-bit re solution 2 channels crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant x/y converter 16 bits x 16 bits i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 81 (8-bit external bus width) 73 (16-bit external bus width) with selectable pull-up resistor ? n channel open drain ports: 2 operating frequency / supply voltage 32 mhz: vcc1 = 4.2 to 5.5 v, vcc2 = 3.0 to vcc1 24 mhz: vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 to vcc1 current consumption 28 ma (32 mhz / vcc1 = vcc2 = 5 v) 22 ma (24 mhz / vcc1 = vcc2 = 3.3 v) 45 a (approx. 1 mhz / vcc1 = vcc2 = 3.3 v, on-chip oscillator low- power consumption mode wait mode) 0.8 a (vcc1 = vcc2 = 3.3 v, stop mode) operating ambient temperature ( c) -20 to 85 c, -40 to 85 c (optional) (2) package 144-pin lqfp (plqp0144ka-a) m32c/8a group rev.1.10 jul 15, 2007 page 4 of 65 table 1.3 specifications (100-pin version) (1) item function specification cpu central processing unit m32c/80 core (multiplier: 16 bits 16 bits 32 bits, multiply-addition operation instructions: 16 16 + 48 48 bits) ? basic instructions: 108 ? minimum instruction execution time: 31.3 ns (f(cpu) = 32 mhz / vcc1 = 4.2 to 5.5 v) 41.7 ns (f(cpu) = 24 mhz / vcc1 = 3.0 to 5.5 v) ? operating mode: microprocessor mode memory rom, ram see table 1.5 product list . power supply voltage detection vdet3 detection functi on, vdet4 detection function, cold start/warm start determination function external bus expansion bus / memory expansion function ? address space: 16 mbyte ? external bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 v and 5 v interfaces ? bus format: switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) clock clock generation circuits ? 4 circuits: main clock, sub clock, on-chip oscillator, pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop detectio n function ? frequency divider circuit: dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 ? low power consumption features: wait mode, stop mode interrupts ? interrupt vectors: 70 ? external interrupt inputs: nmi 1 int 3 (16-bit external bus width) int 6 (8- bit external bus width) key input 4 ? interrupt priority levels: 7 watchdog timer 15-bit 1 (with prescaler) dma dmac ? 4 channels, cycle steal method ? trigger sources: 31 ? transfer modes: 2 (single transfer and repeat transfer) dmacii ? can be activated by all peripheral function interrupt sources ? transfer modes: 2 (single transfer and burst transfer) ? immediate transfer, calculation transfer, and chain transfer functions timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse width modulation (pwm) mode event counter 2-phase pulse signal processing (2-phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode timer function for 3-phase motor control 3-phase inverter control 1 (using timer a1, timer a2, timer a4, and timer b2) on-chip dead time timer m32c/8a group rev.1.10 jul 15, 2007 page 5 of 65 table 1.4 specifications (100-pin version) (2) notes: 1. iebus is a registered trademark of nec electronics corporation. 2. please contact a renesas sales office for optional features. item function specification serial interface uart0 to uart4 clock synchr onous / asynchronous 5 i 2 c bus (optional) (2) , special mode 2, gci mode, sim mode iebus (optional) (1)(2) a/d converter 10-bit resolution x 10 channels, includes sample and hold function d/a converter 8-bit re solution 2 channels crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant x/y converter 16 bits x 16 bits i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 45 (8-bit external bus width) 37 (16-bit external bus width) with selectable pull-up resistor ? n channel open drain ports: 2 operating frequency / supply voltage 32 mhz: vcc1 = 4.2 to 5.5 v, vcc2 = 3.0 to vcc1 24 mhz: vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 to vcc1 current consumption 28 ma (32 mhz / vcc1 = vcc2 = 5 v) 22 ma (24 mhz / vcc1 = vcc2 = 3.3 v) 45 a (approx. 1 mhz / vcc1 = vcc2 = 3.3 v, on-chip oscillator low- power consumption mode wait mode) 0.8 a (vcc1 = vcc2 = 3.3 v, stop mode) operating ambient temperature ( c) -20 to 85 c, -40 to 85 c (optional) (2) package 100-pin lqfp (plqp0100kb-a) m32c/8a group rev.1.10 jul 15, 2007 page 6 of 65 1.2 product list table 1.5 lists product information. figure 1.1 shows product numbering system. table 1.5 product list (m32c/8a) current as of july. 2007 (p): under planning figure 1.1 product numbering system type no. package rom capacity ram capacity remarks m308a0sgp plqp0100kb-a (100p6q-a) ? 12kb romless m308a3sgp (p) plqp0100kb-a (100p6q-a) 24kb romless m308a5sgp (p) plqp0144ka-a (144p6q-a) 24kb romless part no. m30 8a x s gp package type option gp: package plqp0100kb-a (100p6q-a) package plqp0144ka-a (144p6q-a) memory type s: romless version shows ram capacity, pin count, etc. (the value itself has no specific meaning) m32c/8a group m16c family m32c/8a group rev.1.10 jul 15, 2007 page 7 of 65 1.3 block diagram figure 1.2 shows a m32c/8a group block diagram. figure 1.2 m32c/8a group block diagram port p0 8-bit d/a converters: 2 circuits serial interface: 5 channels clock synchronous/ asynchronous x/y converter: 16 bits 16 bits crc calculation circuit x 16 + x 12 + x 5 + 1 (ccitt) 10-bit a/d converter: 1 circuit, 18 input (3) port p13 port p12 port p11 ram multiplier flg isp intb usp pc svf svp vct m32c/8a group rev.1.10 jul 15, 2007 page 8 of 65 1.4 pin assignments figures 1.3 and 1.4 show a pin assignment (top view). figure 1.3 pin assignment for 144-pin package 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 m32c/8a group plqp0144ka-a (144p6q-a) (top view) m32c/8a group rev.1.10 jul 15, 2007 page 9 of 65 table 1.6 144-pin version list of pin names (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 1 p9_6 txd4/sda4/srxd4 anex1 2 p9_5 clk4 anex0 3 p9_4 tb4in cts4 /rts4 /ss4 da1 4 p9_3 tb3in cts3 /rts3 /ss3 da0 5 p9_2 tb2in txd3/sda3/srxd3 6 p9_1 tb1in rxd3/scl3/stxd3 7 p9_0 tb0in clk3 8 p14_6 9 p14_5 10 p14_4 11 p14_3 12 p14_2 13 p14_1 14 p14_0 15 byte 16 cnvss 17 xcin p8_7 18 xcout p8_6 19 reset 20 xout 21 vss 22 xin 23 vcc1 24 p8_5 nmi 25 p8_4 int2 26 p8_3 int1 27 p8_2 int0 28 p8_1 ta4in/u 29 p8_0 ta4out/u 30 p7_7 ta3in 31 p7_6 ta3out 32 p7_5 ta2in/w 33 p7_4 ta2out/w 34 p7_3 ta1in/v cts2 /rts2 /ss2 35 p7_2 ta1out/v clk2 36 p7_1 ta0in/tb5in rxd2/scl2/stxd2 37 p7_0 ta0out txd2/sda2/srxd2 38 p6_7 txd1/sda1/srxd1 39 vcc1 40 p6_6 rxd1/scl1/stxd1 41 vss 42 p6_5 clk1 43 p6_4 cts1 /rts1 /ss1 44 p6_3 txd0/sda0/srxd0 45 p6_2 rxd0/scl0/stxd0 46 p6_1 clk0 47 p6_0 cts0 /rts0 /ss0 48 p13_7 49 p13_6 50 p13_5 m32c/8a group rev.1.10 jul 15, 2007 page 10 of 65 table 1.7 144-pin version list of pin names (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 51 p13_4 52 p5_7 rdy 53 p5_6 ale 54 p5_5 hold 55 p5_4 hlda /ale 56 p13_3 57 vss 58 p13_2 59 vcc2 60 p13_1 61 p13_0 62 clkout p5_3 bclk/ale 63 p5_2 rd 64 p5_1 wrh /bhe 65 p5_0 wrl /wr 66 p12_7 67 p12_6 68 p12_5 69 p4_7 cs0 /a23 70 p4_6 cs1 /a22 71 p4_5 cs2 /a21 72 p4_4 cs3 /a20 73 p4_3 a19 74 vcc2 75 p4_2 a18 76 vss 77 p4_1 a17 78 p4_0 a16 79 p3_7 a15,[a15/d15] 80 p3_6 a14,[a14/d14] 81 p3_5 a13,[a13/d13] 82 p3_4 a12,[a12/d12] 83 p3_3 a11,[a11/d11] 84 p3_2 a10,[a10/d10] 85 p3_1 a9,[a9/d9] 86 p12_4 87 p12_3 88 p12_2 89 p12_1 90 p12_0 91 vcc2 92 p3_0 a8,[a8/d8] 93 vss 94 p2_7 a7,[a7/d7] 95 p2_6 a6,[a6/d6] 96 p2_5 a5,[a5/d5] 97 p2_4 a4,[a4/d4] 98 p2_3 a3,[a3/d3] 99 p2_2 a2,[a2/d2] 100 p2_1 a1,[a1/d1] m32c/8a group rev.1.10 jul 15, 2007 page 11 of 65 table 1.8 144-pin version list of pin names (3) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 101 p2_0 a0,[a0/d0] 102 p1_7 int5 d15 103 p1_6 int4 d14 104 p1_5 int3 d13 105 p1_4 d12 106 p1_3 d11 107 p1_2 d10 108 p1_1 d9 109 p1_0 d8 110 p0_7 d7 111 p0_6 d6 112 p0_5 d5 113 p0_4 d4 114 p11_4 115 p11_3 116 p11_2 117 p11_1 118 p11_0 119 p0_3 d3 120 p0_2 d2 121 p0_1 d1 122 p0_0 d0 123 p15_7 an15_7 124 p15_6 an15_6 125 p15_5 an15_5 126 p15_4 an15_4 127 p15_3 an15_3 128 p15_2 an15_2 129 p15_1 an15_1 130 vss 131 p15_0 an15_0 132 vcc1 133 p10_7 ki3 an_7 134 p10_6 ki2 an_6 135 p10_5 ki1 an_5 136 p10_4 ki0 an_4 137 p10_3 an_3 138 p10_2 an_2 139 p10_1 an_1 140 avss 141 p10_0 an_0 142 vref 143 avcc 144 p9_7 rxd4/scl4/stxd4 adtrg m32c/8a group rev.1.10 jul 15, 2007 page 12 of 65 figure 1.4 pin assignment for 100-pin package 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 m32c/8a group plqp0100kb-a (100p6q-a) (top view) m32c/8a group rev.1.10 jul 15, 2007 page 13 of 65 table 1.9 100-pin version list of pin names (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 1 p9_4 tb4in cts4 /rts4 /ss4 da1 2 p9_3 tb3in cts3 /rts3 /ss3 da0 3 p9_2 tb2in txd3/sda3/srxd3 4 p9_1 tb1in rxd3/scl3/stxd3 5 p9_0 tb0in clk3 6byte 7 cnvss 8 xcin p8_7 9 xcout p8_6 10 reset 11 xout 12 vss 13 xin 14 vcc1 15 p8_5 nmi 16 p8_4 int2 17 p8_3 int1 18 p8_2 int0 19 p8_1 ta4in/u 20 p8_0 ta4out/u 21 p7_7 ta3in 22 p7_6 ta3out 23 p7_5 ta2in/w 24 p7_4 ta2out/w 25 p7_3 ta1in/v cts2 /rts2 /ss2 26 p7_2 ta1out/v clk2 27 p7_1 ta0in/tb5in rxd2/scl2/stxd2 28 p7_0 ta0out txd2/sda2/srxd2 29 p6_7 txd1/sda1/srxd1 30 p6_6 rxd1/scl1/stxd1 31 p6_5 clk1 32 p6_4 cts1 /rts1 /ss1 33 p6_3 txd0/sda0/srxd0 34 p6_2 rxd0/scl0/stxd0 35 p6_1 clk0 36 p6_0 cts0 /rts0 /ss0 37 p5_7 rdy 38 p5_6 ale 39 p5_5 hold 40 p5_4 hlda /ale 41 clkout p5_3 bclk/ale 42 p5_2 rd 43 p5_1 wrh /bhe 44 p5_0 wrl /wr 45 p4_7 cs0 /a23 46 p4_6 cs1 /a22 47 p4_5 cs2 /a21 48 p4_4 cs3 /a20 49 p4_3 a19 50 p4_2 a18 m32c/8a group rev.1.10 jul 15, 2007 page 14 of 65 table 1.10 100-pin version list of pin names (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 51 p4_1 a17 52 p4_0 a16 53 p3_7 a15,[a15/d15] 54 p3_6 a14,[a14/d14] 55 p3_5 a13,[a13/d13] 56 p3_4 a12,[a12/d12] 57 p3_3 a11,[a11/d11] 58 p3_2 a10,[a10/d10] 59 p3_1 a9,[a9/d9] 60 vcc2 61 p3_0 a8,[a8/d8] 62 vss 63 p2_7 a7,[a7/d7] 64 p2_6 a6,[a6/d6] 65 p2_5 a5,[a5/d5] 66 p2_4 a4,[a4/d4] 67 p2_3 a3,[a3/d3] 68 p2_2 a2,[a2/d2] 69 p2_1 a1,[a1/d1] 70 p2_0 a0,[a0/d0] 71 p1_7 int5 d15 72 p1_6 int4 d14 73 p1_5 int3 d13 74 p1_4 d12 75 p1_3 d11 76 p1_2 d10 77 p1_1 d9 78 p1_0 d8 79 p0_7 d7 80 p0_6 d6 81 p0_5 d5 82 p0_4 d4 83 p0_3 d3 84 p0_2 d2 85 p0_1 d1 86 p0_0 d0 87 p10_7 ki3 an_7 88 p10_6 ki2 an_6 89 p10_5 ki1 an_5 90 p10_4 ki0 an_4 91 p10_3 an_3 92 p10_2 an_2 93 p10_1 an_1 94 avss 95 p10_0 an_0 96 vref 97 avcc 98 p9_7 rxd4/scl4/stxd4 adtrg 99 p9_6 txd4/sda4/srxd4 anex1 100 p9_5 clk4 anex0 m32c/8a group rev.1.10 jul 15, 2007 page 15 of 65 1.5 pin functions table 1.11 pin functions (1) (100-pin package and 144-pin package) item pin name i/o type supply voltage description power supply vcc1,vcc2 vss ?? apply 3.0 to 5.5 v to pins vcc1 and vcc2, and 0 v to the vss pin. the input condition of vcc1 vcc2 must be met. analog power supply input avcc avss ? vcc1 power supply input pins to th e a/d converter and d/a converter. connect the avcc pin to vcc1, and the avss pin to vss. reset input reset i vcc1 the mcu is placed in a reset state when applying an ?l? signal to the reset pin. cnvss cnvss i vcc1 this pin switches processor mode. apply an ?h? signal to the cnvss pin to start up in microprocessor mode. external data bus width select input byte i vcc1 this pin switches data bus wid th in external memory space 3. a data bus is 16 bits wide when the byte pin is held ?l? and 8 bits wide when it is held ?h?. bus control pins d0 to d7 i/o vcc2 data (d0 to d7) input/output pins while accessing an external memory space with separate bus. d8 to d15 i/o vcc2 data (d8 to d15) inputs/output pins while accessing an external memory space with 16-bit separate bus. a0 to a22 o vcc2 address bits (a0 to a22) output pins. a23 o vcc2 inverted address bit (a23) output pin. a0/d0 to a7/d7 i/o vcc2 data (d0 to d7) input/output and 8 low-order address bits (a0 to a7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. a8/d8 to a15/d15 i/o vcc2 data (d8 to d15) input/output and 8 middle-order address bits (a8 to a15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. cs0 to cs3 o vcc2 chip-select signal output pins used to specify external devices. wrl /wr wrh /bhe rd o vcc2 wrl , wrh , (wr , bhe ) and rd signal output pins. wrl and wrh can be switched with wr and bhe by program. ?wr l, wrh and rd are selected: if external data bus is 16 bits wide, data is written to an even address in external memory space while an ?l? is output from the wrl pin. data is written to an odd address while an ?l? is output from the wrh pin. data is read while an ?l? is output from the rd pin. ?wr , bhe and rd are selected: data is written while an ?l ? is output from the wr pin. data is read while an ?l? is output from the rd pin. data in odd address is accessed while an ?l? is output from the bhe pin. select wr , bhe and rd when an external data bus is 8 bits wide. ale o vcc2 ale signal is used for the external devices to latch address signals when the multiplexe d bus is selected. hold i vcc2 the mcu is placed in a hold state while an ?l? signal is applied to the hold pin. hlda o vcc2 the hlda pin outputs an ?l? while t he mcu is placed in a hold state rdy i vcc2 bus is placed in a wait state while an ?l? signal is applied to the rdy pin. m32c/8a group rev.1.10 jul 15, 2007 page 16 of 65 table 1.12 pin functions (2) (100-pin package and 144-pin package) item pin name i/o type supply voltage description main clock input xin i vcc1 input/output pins for the main clock oscillation circuit. connect a ceramic resonator or crystal osci llator between xin and xout. to apply an external clock, apply it to xin and leave xout open main clock output xout o vcc1 sub clock input xcin i vcc1 input/output pins for the sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout. to apply an external clock, apply it to xcin and leave xcout open. sub clock output xcout o vcc1 bclk output bclk o vcc2 bus clock output pin clock output clkout o vcc2 the clkout pin outputs the clock having the same frequency as fc, f8, or f32 int interrupt input int0 to int2 i vcc1 int interrupt input pins nt3 to int5 i vcc2 nmi interrupt input nmi i vcc1 nmi interrupt input pin. connect the nmi pin to vcc1 via a resistor when the nmi interrupt is not used. timer a ta0out to ta4out i/o vcc1 timer a0 to a4 input/output pins (ta0out is n-channel open drain output) ta0in to ta4in i vcc1 timer a0 to a4 input pins timer b tb0in to tb5in i vcc1 timer b0 to b5 input pins three-phase motor control timer output u, u , v, v , w, w o vcc1 three-phase motor control timer output pins serial interface cts0 to cts4 i vcc1 input pins to control data transmission rts0 to rts4 o vcc1 output pins to control data reception clk0 to clk4 i/o vcc1 serial clock input/output pins rxd0 to rxd4 i vcc1 serial data input pins txd0 to txd4 o vcc1 serial data output pins (txd2 is n-channel open drain output ) i 2 c mode sda0 to sda4 i/o vcc1 serial data input/output pins (sda2 is n-channel open drain output ) scl0 to scl4 i/o vcc1 serial clock input/output pins (scl2 is n-channel open drain output ) serial interface special function stxd0 to stxd4 o vcc1 serial data output pins when slave mode is selected (stxd2 is n-channel open drain output ) srxd0 to srxd4 i vcc1 serial data input pins when slave mode is selected ss0 to ss4 i vcc1 control input pins used in the serial interface special mode. m32c/8a group rev.1.10 jul 15, 2007 page 17 of 65 table 1.13 pin functions (3) (100-pin package and 144-pin package) note: 1. p0 to p5 function as bus control pins and cannot be us ed as i/o ports. p1_0 to p1_7 can be used as i/o ports when using with 8-bit external bus width only. table 1.14 pin functions (4) (144-pin package only) item pin name i/o type supply voltage description reference voltage input vref i ? the vref pin supplies the reference voltage to the a/d converter and d/a converter. a/d converter an_0 to an_7 i vcc1 analog input pins for the a/d converter. adtrg i vcc1 external trigger input pin for the a/d converter. anex0 i/o vcc1 extended analog input pin for the a/d converter or output pin in external op-amp connection mode. anex1 i vcc1 extended analog input pin for the a/d converter. d/a converter da0, da1 o vcc1 output pins for the d/a converter. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 i/o (1) vcc2 8-bit cmos i/o ports. the port pi direction register determines if each pin is used as an input po rt or an output port. the pull-up control register determines if the input ports, divided into groups of four, are pulled up or not. p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7 i/o vcc1 these 8-bit i/o ports are functionally equivalent to p0. (p7_0 and p7_1 are n-channel open drain output.) p8_0 to p8_4 p8_6, p8_7 these i/o ports are functionally equivalent to p0. input port p8_5 i vcc1 shares the pin with nmi . input port to read nmi pin level. key input interrupt input ki0 to ki3 i vcc1 key input interrupt input pins item pin name i/o type supply voltage description a/d converter an15_0 to an15_7 i vcc1 analog input pins for the a/d converter i/o ports p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 i/o vcc2 these i/o ports are functionally equivalent to p0. p14_0 to p14_6, p15_0 to p15_7 i/o vcc1 m32c/8a group rev.1.10 jul 15, 2007 page 18 of 65 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the register bank is comprised of eight registers (r0, r1, r2, r3, a0, a1, sb, and fb) out of 28 cpu registers. there are two sets of register banks. figure 2.1 cpu register r0h r0l r1h r1l r2 r3 r2 r3 a0 a1 sb fb static base register (1) frame base register (1) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved processor interrupt priority level reserved r0l r1l r2 r3 r2 r3 a0 a1 sb fb usp intb isp pc r0h r1h b31 b15 b23 b0 flg c d z s b o i u ipl b15 b0 b8 b7 svf svp vct b23 b15 b0 dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dra0 dra1 dsa0 dsa1 b23 b15 b0 b7 address registers (1) user stack pointer interrupt stack pointer interrupt table register program counter flag register general registers high-speed interrupt registers dmac-associated registers flag save register pc save register vector register dma mode registers dma transfer count registers dma transfer count reload registers dma memory address registers dma memory address reload registers dma sfr address registers note: 1. these registers comprise a register bank. there are two sets of register banks (register bank 0 and register bank 1). data registers (1) m32c/8a group rev.1.10 jul 15, 2007 page 19 of 65 2.1 general registers 2.1.1 data registers (r0, r1, r2, and r3) r0, r1, r2, and r3 are 16-bit registers for transfer, arith metic and logic operations. r0 and r1 can be split into high-order (r0h/r1h) and low-order bits (r0l/r1l) to be used separately as 8-bit data registers. r0 can be combined with r2 and used as a 32-bit data register (r2r0). the same applies to r3r1. 2.1.2 address registers (a0 and a1) a0 and a1 are 24-bit registers used for a0-/a1-indir ect addressing, a0-/a1-relative addressing, transfer, arithmetic and logic operations. 2.1.3 static base register (sb) sb is a 24-bit register used for sb-relative addressing. 2.1.4 frame base register (fb) fb is a 24-bit register used for fb-relative addressing. 2.1.5 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are 24 bits wide each. the u flag is used to switch between usp and isp. refer to 2.1.8 flag register (flg) for details on the u flag. set usp and isp to even addresses to execute an interrupt sequence efficiently. 2.1.6 interrupt table register (intb) intb is a 24-bit register indicating the starting address of a relocatable interrupt vector table. 2.1.7 program counter (pc) pc is 24 bits wide and indicates the address of the next instruction to be executed. 2.1.8 flag register (flg) flg is a 16-bit register indicating the cpu state. 2.1.8.1 carry flag (c) the c flag indicates whether or no t carry or borrow has been generated after executing an instruction. 2.1.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.1.8.3 zero flag (z) the z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0. 2.1.8.4 sign flag (s) the s flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0. 2.1.8.5 register bank select flag (b) register bank 0 is selected when the b flag is set to 0. register bank 1 is selected when this flag is set to 1. 2.1.8.6 overflow flag (o) the o flag becomes 1 when an arithmetic operat ion results in an overflow; otherwise becomes 0. m32c/8a group rev.1.10 jul 15, 2007 page 20 of 65 2.1.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0 and enabled when it is set to 1. the i flag becomes 0 when an interrupt request is acknowledged. 2.1.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0. usp is selected when the u flag is set to 1. the u flag becomes 0 when a hardware interrupt reque st is acknowledged or the int instruction specifying software interrupt numbers 0 to 31 is executed. 2.1.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priority than ipl, the interrupt is enabled. 2.1.8.10 reserved space only write 0 to bits assigned to the reserved space. when read, the bits return undefined values. 2.2 high-speed interrupt registers registers associated with the hi gh-speed interrupt are follows: ? save flag register (svf) ? save pc register (svp) ? vector register (vct) 2.3 dmac-associated registers registers associated with the dmac are as follows: ? dma mode register (dmd0, dmd1) ? dma transfer count register (dct0, dct1) ? dma transfer count reload register (drc0, drc1) ? dma memory address register (dma0, dma1) ? dma memory address reload register (dra0, dra1) ? dma sfr address register (dsa0, dsa1) m32c/8a group rev.1.10 jul 15, 2007 page 21 of 65 3. memory figure 3.1 is a memory map of the m32c/8a group. the m32c/8a group has 16-mbyte address space from addresses 000000h to ffffffh. the fixed interrupt vectors are allocated addresses ffffdch to ffffffh. th ey store the starting address of each interrupt routine. the internal ram is allocated higher addresses, beginn ing with address 000400h. for example, a 12-kbyte internal ram area is allocated addresses 000400h to 0033ffh. the internal ram is used not only for storing data but for the stacks when subroutines are called or wh en interrupt requests are acknowledged. sfrs are allocated address 000000h to 0003ffh. the peripheral function control registers such as for i/o ports, a/d converters, serial interfaces, timers are allocated here. all blank spaces w ithin sfrs are reserved and cannot be accessed by users. the special page vectors are allocated addresses fffe00h to ffffdbh. they are used for the jmps instruction and jsrs instruction. refer to the renesas publication m32c/80 series software manual for details. figure 3.1 memory map note: 1. the watchdog timer interr upt, oscillation stop detection interrupt , and vdet4 detection interrupt use the same vector. ffffffh special page vector table ffffdch fffe00h reset address match brk instruction overflow undefined instruction nmi watchdog timer (1) 000000h sfr internal ram reserved external space 000400h xxxxxxh 010000h ffffffh internal ram xxxxxxh 0033ffh capacity 12 kbytes 0063ffh 24 kbytes m32c/8a group rev.1.10 jul 15, 2007 page 22 of 65 4. special function registers (sfrs) special function registers (sfrs) are the control registers of peripheral functions . tables 4.1 to 4.11 list sfr address maps. table 4.1 sfr address map (1) x: undefined blank spaces are all reserved. no access is allowed. note: 1. bits pm01 and pm00 in the pm0 register maintain values set before reset, even after software reset or watchdog timer reset ha s been performed. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 (1) pm0 0000 0011b(cnvss=?h?) 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 0000 1000b 0007h system clock control register 1 cm1 0010 0000b 0008h 0009h address match interrupt enable register aier 00h 000ah protect register prcr xxxx 0000b 000bh external data bus width control register ds xxxx 1000b(byte=?l?) xxxx 0000b(byte=?h?) 000ch main clock division register mcd xxx0 1000b 000dh oscillation stop detection register cm2 00h 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00xx xxxxb 0010h address match interrupt register 0 rmad0 000000h 0011h 0012h 0013h processor mode register 2 pm2 00h 0014h address match interrupt register 1 rmad1 000000h 0015h 0016h 0017h voltage detection register 2 vcr2 00h 0018h address match interrupt register 2 rmad2 000000h 0019h 001ah 001bh voltage detection register 1 vcr1 0000 1000b 001ch address match interrupt register 3 rmad3 000000h 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h pll control register 0 plc0 0001 x010b 0027h pll control register 1 plc1 000x 0000b 0028h address match interrupt register 4 rmad4 000000h 0029h 002ah 002bh 002ch address match interrupt register 5 rmad5 000000h 002dh 002eh 002fh vdet4 detection interrupt register d4int xx00 0000b m32c/8a group rev.1.10 jul 15, 2007 page 23 of 65 table 4.2 sfr address map (2) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h address match interrupt register 6 rmad6 000000h 0039h 003ah 003bh 003ch address match interrupt register 7 rmad7 000000h 003dh 003eh 003fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h external space wait control register 0 ewcr0 x0x0 0011b 0049h external space wait control register 1 ewcr1 x0x0 0011b 004ah external space wait control register 2 ewcr2 x0x0 0011b 004bh external space wait control register 3 ewcr3 x0x0 0011b 004ch page mode wait control register 0 pwcr0 0001 0001b 004dh page mode wait control register 1 pwcr1 0001 0001b 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh m32c/8a group rev.1.10 jul 15, 2007 page 24 of 65 table 4.3 sfr address map (3) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h dma0 interrupt control register dm0ic xxxx x000b 0069h timer b5 interrupt control register tb5ic xxxx x000b 006ah dma2 interrupt control register dm2ic xxxx x000b 006bh uart2 receive/ack interrupt control register s2ric xxxx x000b 006ch timer a0 interrupt control register ta0ic xxxx x000b 006dh uart3 receive/ack interrupt control register s3ric xxxx x000b 006eh timer a2 interrupt control register ta2ic xxxx x000b 006fh uart4 receive/ack interrupt control register s4ric xxxx x000b 0070h timer a4 interrupt control register ta4ic xxxx x000b 0071h uart0/uart3 bus conflict detection interrupt control register bcn0ic/bcn3ic xxxx x000b 0072h uart0 receive/ack interrupt control register s0ric xxxx x000b 0073h a/d0 conversion interrupt control register ad0ic xxxx x000b 0074h uart1 receive/ack interrupt control register s1ric xxxx x000b 0075h 0076h timer b1 interrupt control register tb1ic xxxx x000b 0077h 0078h timer b3 interrupt control register tb3ic xxxx x000b 0079h 007ah int5 interrupt control register int5ic xx00 x000b 007bh 007ch int3 interrupt control register int3ic xx00 x000b 007dh 007eh int1 interrupt control register int1ic xx00 x000b 007fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dma1 interrupt control register dm1ic xxxx x000b 0089h uart2 transmit/nack interrupt control register s2tic xxxx x000b 008ah dma3 interrupt control register dm3ic xxxx x000b 008bh uart3 transmit/nack interrupt control register s3tic xxxx x000b 008ch timer a1 interrupt control register ta1ic xxxx x000b 008dh uart4 transmit/nack interrupt control register s4tic xxxx x000b 008eh timer a3 interrupt control register ta3ic xxxx x000b 008fh uart2 bus conflict detection interrupt control register bcn2ic xxxx x000b m32c/8a group rev.1.10 jul 15, 2007 page 25 of 65 table 4.4 sfr address map (4) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0090h uart0 transmit/nack interrupt control register s0tic xxxx x000b 0091h uart1/uart4 bus conflict detection interrupt control register bcn1ic/bcn4ic xxxx x000b 0092h uart1 transmit/nack interrupt control register s1tic xxxx x000b 0093h key input interrupt control register kupic xxxx x000b 0094h timer b0 interrupt control register tb0ic xxxx x000b 0095h 0096h timer b2 interrupt control register tb2ic xxxx x000b 0097h 0098h timer b4 interrupt control register tb4ic xxxx x000b 0099h 009ah int4 interrupt control register int4ic xx00 x000b 009bh 009ch int2 interrupt control register int2ic xx00 x000b 009dh 009eh int0 interrupt control register int0ic xx00 x000b 009fh exit priority register rlvl xxxx 0000b 00a0h 00a1h 00a2h 00a3h 00a4h 00a5h 00a6h 00a7h 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh to 02bfh m32c/8a group rev.1.10 jul 15, 2007 page 26 of 65 table 4.5 sfr address map (5) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 02c0h x0 register, y0 register x0r, y0r xxxxh 02c1h 02c2h x1 register, y1 register x1r , y1r xxxxh 02c3h 02c4h x2 register, y2 register x2r , y2r xxxxh 02c5h 02c6h x3 register, y3 register x3r , y3r xxxxh 02c7h 02c8h x4 register, y4 register x4r , y4r xxxxh 02c9h 02cah x5 register, y5 register x5r , y5r xxxxh 02cbh 02cch x6 register, y6 register x6r , y6r xxxxh 02cdh 02ceh x7 register, y7 register x7r , y7r xxxxh 02cfh 02d0h x8 register, y8 register x8r , y8r xxxxh 02d1h 02d2h x9 register, y9 register x9r , y9r xxxxh 02d3h 02d4h x10 register, y10 register x10r , y10r xxxxh 02d5h 02d6h x11 register, y11 register x11r , y11r xxxxh 02d7h 02d8h x12 register, y12 register x12r , y12r xxxxh 02d9h 02dah x13 register, y13 register x13r , y13r xxxxh 02dbh 02dch x14 register, y14 register x14r , y14r xxxxh 02ddh 02deh x15 register, y15 register x15r , y15r xxxxh 02dfh 02e0h x/y control register xyc xxxx xx00b 02e1h 02e2h 02e3h 02e4h uart1 special mode register 4 u1smr4 00h 02e5h uart1 special mode register 3 u1smr3 00h 02e6h uart1 special mode register 2 u1smr2 00h 02e7h uart1 special mode register u1smr 00h 02e8h uart1 transmit/receive mode register u1mr 00h 02e9h uart1 baud rate register u1brg xxh 02eah uart1 transmit buffer register u1tb xxxxh 02ebh 02ech uart1 transmit/receive control register 0 u1c0 0000 1000b 02edh uart1 transmit/receive control register 1 u1c1 0000 0010b 02eeh uart1 receive buffer register u1rb xxxxh 02efh m32c/8a group rev.1.10 jul 15, 2007 page 27 of 65 table 4.6 sfr address map (6) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 02f0h 02f1h 02f2h 02f3h 02f4h uart4 special mode register 4 u4smr4 00h 02f5h uart4 special mode register 3 u4smr3 00h 02f6h uart4 special mode register 2 u4smr2 00h 02f7h uart4 special mode register u4smr 00h 02f8h uart4 transmit/receive mode register u4mr 00h 02f9h uart4 baud rate register u4brg xxh 02fah uart4 transmit buffer register u4tb xxxxh 02fbh 02fch uart4 transmit/receive control register 0 u4c0 0000 1000b 02fdh uart4 transmit/receive control register 1 u4c1 0000 0010b 02feh uart4 receive buffer register u4rb xxxxh 02ffh 0300h timer b3, b4, b5 count start register tbsr 000x xxxxb 0301h 0302h timer a11 register ta11 xxxxh 0303h 0304h timer a21 register ta21 xxxxh 0305h 0306h timer a41 register ta41 xxxxh 0307h 0308h three-phase pwm control register 0 invc0 00h 0309h three-phase pwm control register 1 invc1 00h 030ah three-phase output buffer register 0 idb0 xx11 1111b 030bh three-phase output buffer register 1 idb1 xx11 1111b 030ch dead time timer dtt xxh 030dh timer b2 interrupt generation frequency set counter ictb2 xxh 030eh 030fh 0310h timer b3 register tb3 xxxxh 0311h 0312h timer b4 register tb4 xxxxh 0313h 0314h timer b5 register tb5 xxxxh 0315h 0316h 0317h 0318h 0319h 031ah 031bh timer b3 mode register tb3mr 00xx 0000b 031ch timer b4 mode register tb4mr 00xx 0000b 031dh timer b5 mode register tb5mr 00xx 0000b 031eh 031fh external interrupt source select register ifsr 00h m32c/8a group rev.1.10 jul 15, 2007 page 28 of 65 table 4.7 sfr address map (7) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 0320h 0321h 0322h 0323h 0324h uart3 special mode register 4 u3smr4 00h 0325h uart3 special mode register 3 u3smr3 00h 0326h uart3 special mode register 2 u3smr2 00h 0327h uart3 special mode register u3smr 00h 0328h uart3 transmit/receive mode register u3mr 00h 0329h uart3 baud rate register u3brg xxh 032ah uart3 transmit buffer register u3tb xxxxh 032bh 032ch uart3 transmit/receive control register 0 u3c0 0000 1000b 032dh uart3 transmit/receive control register 1 u3c1 0000 0010b 032eh uart3 receive buffer register u3rb xxxxh 032fh 0330h 0331h 0332h 0333h 0334h uart2 special mode register 4 u2smr4 00h 0335h uart2 special mode register 3 u2smr3 00h 0336h uart2 special mode register 2 u2smr2 00h 0337h uart2 special mode register u2smr 00h 0338h uart2 transmit/receive mode register u2mr 00h 0339h uart2 baud rate register u2brg xxh 033ah uart2 transmit buffer register u2tb xxxxh 033bh 033ch uart2 transmit/receive control register 0 u2c0 0000 1000b 033dh uart2 transmit/receive control register 1 u2c1 0000 0010b 033eh uart2 receive buffer register u2rb xxxxh 033fh 0340h count start register tabsr 00h 0341h clock prescaler reset register cpsrf 0xxx xxxxb 0342h one-shot start register onsf 00h 0343h trigger select register trgsr 00h 0344h up/down select register udf 00h 0345h 0346h timer a0 register ta0 xxxxh 0347h 0348h timer a1 register ta1 xxxxh 0349h 034ah timer a2 register ta2 xxxxh 034bh 044ch timer a3 register ta3 xxxxh 034dh 034eh timer a4 register ta4 xxxxh 034fh m32c/8a group rev.1.10 jul 15, 2007 page 29 of 65 table 4.8 sfr address map (8) x: undefined blank spaces are all rese rved. no access is allowed. note: 1. the tcspr register maintains values set before reset, even after software reset or watchdog timer reset has been performed. address register symbol after reset 0350h timer b0 register tb0 xxxxh 0351h 0352h timer b1 register tb1 xxxxh 0353h 0354h timer b2 register tb2 xxxxh 0355h 0356h timer a0 mode register ta0mr 00h 0357h timer a1 mode register ta1mr 00h 0358h timer a2 mode register ta2mr 00h 0359h timer a3 mode register ta3mr 00h 035ah timer a4 mode register ta4mr 00h 035bh timer b0 mode register tb0mr 00xx 0000b 035ch timer b1 mode register tb1mr 00xx 0000b 035dh timer b2 mode register tb2mr 00xx 0000b 035eh timer b2 special mode register tb2sc xxxx xxx0b 035fh count source prescaler register (1) tcspr 0xxx 0000b 0360h 0361h 0362h 0363h 0364h uart0 special mode register 4 u0smr4 00h 0365h uart0 special mode register 3 u0smr3 00h 0366h uart0 special mode register 2 u0smr2 00h 0367h uart0 special mode register u0smr 00h 0368h uart0 transmit/receive mode register u0mr 00h 0369h uart0 baud rate register u0brg xxh 036ah uart0 transmit buffer register u0tb xxxxh 036bh 036ch uart0 transmit/receive control register 0 u0c0 0000 1000b 036dh uart0 transmit/receive control register 1 u0c1 0000 0010b 036eh uart0 receive buffer register u0rb xxxxh 036fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h dma0 request source select register dm0sl 0x00 0000b 0379h dma1 request source select register dm1sl 0x00 0000b 037ah dma2 request source select register dm2sl 0x00 0000b 037bh dma3 request source select register dm3sl 0x00 0000b 037ch crc data register crcd xxxxh 037dh 037eh crc input register crcin xxh 037fh m32c/8a group rev.1.10 jul 15, 2007 page 30 of 65 table 4.9 sfr address map (9) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 0380h a/d0 register 0 ad00 00xxh 0381h 0382h a/d0 register 1 ad01 00xxh 0383h 0384h a/d0 register 2 ad02 00xxh 0385h 0386h a/d0 register 3 ad03 00xxh 0387h 0388h a/d0 register 4 ad04 00xxh 0389h 038ah a/d0 register 5 ad05 00xxh 038bh 038ch a/d0 register 6 ad06 00xxh 038dh 038eh a/d0 register 7 ad07 00xxh 038fh 0390h 0391h 0392h a/d0 control register 4 ad0con4 xxxx 00xxb 0393h 0394h a/d0 control register 2 ad0con2 xx0x x000b 0395h a/d0 control register 3 ad0con3 xxxx x000b 0396h a/d0 control register 0 ad0con0 00h 0397h a/d0 control register 1 ad0con1 00h 0398h d/a register 0 da0 xxh 0399h 039ah d/a register 1 da1 xxh 039bh 039ch d/a control register dacon xxxx xx00b 039dh 039eh 039fh m32c/8a group rev.1.10 jul 15, 2007 page 31 of 65 table 4.10 sfr address map (10) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. these registers cannot be used in the 100-pin package. 2. set to ffh in the 100-pin package. address register address register 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh function select register c psc 00x0 0000b 03b0h function select register a0 ps0 00h 03b1h function select register a1 ps1 00h 03b2h function select register b0 psl0 00h 03b3h function select register b1 psl1 00h 03b4h function select register a2 ps2 00x0 0000b 03b5h function select register a3 ps3 00h 03b6h function select register b2 psl2 00x0 0000b 03b7h function select register b3 psl3 00h 03b8h 03b9h 03bah 03bbh 03bch 03bdh 03beh 03bfh 03c0h port p6 register p6 xxh 03c1h port p7 register p7 xxh 03c2h port p6 direction register pd6 00h 03c3h port p7 direction register pd7 00h 03c4h port p8 register p8 xxh 03c5h port p9 register p9 xxh 03c6h port p8 direction register pd8 00x0 0000b 03c7h port p9 direction register pd9 00h 03c8h port p10 register p10 xxh 03c9h port p11 register (1) p11 xxh 03cah port p10 direction register pd10 00h 03cbh port p11 direction register (1)(2) pd11 xxx0 0000b 03cch port p12 register (1) p12 xxh 03cdh port p13 register (1) p13 xxh 03ceh port p12 direction register (1)(2) pd12 00h 03cfh port p13 direction register (1)(2) pd13 00h m32c/8a group rev.1.10 jul 15, 2007 page 32 of 65 table 4.11 sfr address map (11) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. these registers cannot be used in the 100-pin package. 2. set to ffh in the 100-pin package. 3. set to 00h in the 100-pin package. address register address register 03d0h port p14 register (1) p14 xxh 03d1h port p15 register (1) p15 xxh 03d2h port p14 direction register (1)(2) pd14 x000 0000b 03d3h port p15 direction register (1)(2) pd15 00h 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah pull-up control register 2 pur2 00h 03dbh pull-up control register 3 pur3 00h 03dch pull-up control register 4 (1)(3) pur4 xxxx 0000b 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech 03edh 03eeh 03efh 03f0h pull-up control register 0 pur0 00h 03f1h pull-up control register 1 pur1 xxxx 0000b 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh port control register pcr xxxx xxx0b m32c/8a group rev.1.10 jul 15, 2007 page 33 of 65 5. electrical characteristics table 5.1 absolute maximum ratings notes: 1. p11 to p15 are provided in the 144-pin package only. 2. contact a renesas sales office if temperature range of -40 to 85 c is required. symbol parameter condition value unit vcc1, vcc2 supply voltage vcc1 = avcc -0.3 to 6.0 v vcc2 supply voltage ? -0.3 to vcc1 + 0.1 v avcc analog supply voltage vcc1 = avcc -0.3 to 6.0 v vi input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) , vref, xin -0.3 to vcc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) -0.3 to vcc2 + 0.3 p7_0, p7_1 -0.3 to 6.0 vo output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p14_0 to 14_6, p15_0 to p15_7 (1) , xout -0.3 to vcc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) -0.3 to vcc2 + 0.3 p7_0, p7_1 -0.3 to 6.0 pd power dissipation -40 c topr 85 c 500 mw topr operating ambient temperature -20 to 85/ -40 to 85 (2) c tstg storage temperature -65 to 150 c m32c/8a group rev.1.10 jul 15, 2007 page 34 of 65 table 5.2 recommended operating conditions (1) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified) notes: 1. vih and vil reference for p8_7 apply when p8_7 is us ed as a programmable input port. it does not apply when p8_7 is used as xcin. 2. p11 to p15 are provided in the 144-pin package only. symbol parameter standard unit min. typ. max. vcc1, vcc2 supply voltage (vcc1 vcc2) 3.0 5.0 5.5 v avcc analog supply voltage vcc1 v vss supply voltage 0 v avss analog supply voltage 0 v vih input high ?h? voltage p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (2) 0.8vcc2 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7 (1) , p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (2) , xin, reset , cnvss, byte 0.8vcc1 vcc1 p7_0, p7_1 0.8vcc1 6.0 p0_0 to p0_7, p1_0 to p1_7 (in microprocessor mode) 0.5vcc2 vcc2 vil input low ?l? voltage p2_0 to p2_7,p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (2) 0 0.2vcc2 v p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (1) , p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (2) , xin, reset , cnvss, byte 0 0.2vcc1 p0_0 to p0_7, p1_0 to p1_7 (in microprocessor mode) 0 0.16vcc2 m32c/8a group rev.1.10 jul 15, 2007 page 35 of 65 table 5.3 recommended operating conditions (2) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified notes: 1. average output current is the average value within 100 ms. 2. a total iol(peak) of p0, p1, p2, p8_6, p8_7, p9, p10, p11, p14, and p15 must be 80 ma or less. a total iol(peak) of p3, p4, p5, p6, p7,p8_0 to p8_4, p12, and p13 must be 80 ma or less. a total ioh(peak) of p0, p1, p2, and p11 must be -40 ma or less. a total ioh(peak) of p8_6 to p8_7, p9, p 10, p14, and p15 must be -40 ma or less. a total ioh(peak) of p3, p4, p5, p12, and p13 must be -40 ma or less. a total ioh(peak) of p6, p7, and p8_0 to p8_4 must be -40 ma or less. 3. p11 to p15 are provided in the 144-pin package only. symbol parameter standard unit min. typ. max. ioh(peak) peak output high ?h? current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) -10.0 ma ioh(avg) average output ?h? current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) -5.0 ma iol(peak) peak output ?l? current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) 10.0 ma iol(avg) average output ?l? current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) 5.0 ma m32c/8a group rev.1.10 jul 15, 2007 page 36 of 65 table 5.4 recommended operating conditions (3) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified) symbol parameter standard unit min. typ. max. f(cpu) cpu clock frequency (same frequency as f(bclk)) vcc1 = 4.2 to 5.5v 0 32 mhz vcc1 = 3.0 to 5.5v 0 24 mhz f(xin) main clock input frequency vcc1 = 4.2 to 5.5v 0 32 mhz vcc1 = 3.0 to 5.5v 0 24 mhz f(xcin) sub clock frequency 32.768 50 khz f(ring) on-chip oscillator frequency 0.5 1 2 mhz f(vco) vco clock frequency (pll frequency synthesizer) 20 80 mhz f(pll) pll clock frequency vcc1 = 4.2 to 5.5v 10 32 mhz vcc1 = 3.0 to 5.5v 10 24 mhz tsu(pll) wait time to stabilize pll frequency synthesizer vcc1 = 5.0v 5 ms vcc1 = 3.3v 10 ms m32c/8a group rev.1.10 jul 15, 2007 page 37 of 65 table 5.5 electrical characteristics (1) (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 32 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter condition standard unit min. typ. max. voh output high ?h? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -5 ma vcc2 - 2.0 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) ioh = -5 ma vcc1 - 2.0 vcc1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7 p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -200 a vcc2 - 0.3 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) ioh = -200 a vcc1 - 0.3 vcc1 xout ioh = -1 ma 3.0 vcc1 v xcout high drive capability no load applied 2.5 v low drive capability no load applied 1.6 v vol output low ?l? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 200 a0.45v xout iol = 1 ma 2.0 v xcout high drive capability no load applied 0v low drive capability no load applied 0v vt+ - vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int 5 , adtrg , cts0 to cts 4 , clk0 to clk4, ta0out to ta4out, nmi , ki0 to ki3 , rxd0 to rxd4, scl0 to scl4, sda0 to sda4 0.2 1.0 v reset 0.2 1.8 v vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 38 of 65 table 5.6 electrical characteristics (2) (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 32 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. table 5.7 electrical characte ristics (3) (vcc1 = vcc2 = 5.5 v, vss = 0 v, topr = 25 c ) symbol parameter condition standard unit min. typ. max. iih input high ?h? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 5 v 5.0 a iil input low ?l? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 0v -5.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) vi = 0v 20 40 167 k rfxin feedback resistance xin 1.5 m rfxcin feedback resistance xcin 10 m vram ram data retention voltage in stop mode 2.0 v symbol parameter condition standard unit min. typ. max. icc power supply current romless version f(cpu) = 32 mhz 28 45 ma f(cpu) = 16 mhz 16 ma f(cpu) = 8 mhz 10 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 1ma f(cpu) = 32 khz in low-power consumption mode 25 a f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 50 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 39 of 65 table 5.8 a/d conversion characteristics (vcc1 = vcc2 = avcc = vref = 4.2 to 5. 5 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 32mhz unless otherwise specified) notes: 1. the value is obtained when ad frequency is at 16 mhz. keep ad frequency at 16 mhz or less. 2. with using the sample and hold function note: 1. measured when one d/a converter is used, and the dai regist er (i = 0, 1) of the unused d/a converter is set to 00h. the current flown into the resist or ladder in the a/d converter is excl uded. ivref flows even if the vcut bit in the ad0con1 register is set to 0 (vref not connected) symbol parameter measurement condition standard unit min. typ. max. ? resolution vref = vcc1 10 bits inl integral nonlinearity error vref = vcc1 = vcc2 = 5 v an_0 to an_7, an15_0 to an15_7, anex0, anex1 3 lsb external op-amp connection mode 7 lsb dnl differential nonlinearity error 1 lsb ? offset error 3 lsb ? gain error 3 lsb rladder resistor ladder vref = vcc1 8 40 k tconv 10-bit conversion time (1)(2) 2.06 s tconv 8-bit conversion time (1)(2) 1.75 s tsamp sampling time (1) 0.188 s vref reference voltage 2 vcc1 v via analog input voltage 0 vref v table 5.9 d/a conversion characteristics (vcc1 = vcc2 = vref = 4.2 to 5.5 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 32mhz unless otherwise specified) symbol parameter measurement condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % tsu setup time 3 s ro output resistance 4 10 20 k ivref reference power supply input current (note 1) 1.5 ma vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 40 of 65 table 5.10 voltage detection circuit electrical characteristics (vcc1 = vcc2 = 3.0 to 5.5 v, vss = 0 v, topr = 25 c unless otherwise specified) notes: 1. vdet4 > vdet3 2. vdet3r > vdet3 is not guaranteed. table 5.11 power supply timing characteristics note: 1. when vcc1= 5 v figure 5.1 power supply timing diagram symbol parameter standard unit min. typ. max. vdet4 vdet4 detection voltage vcc1 = 3.0 v to 5.5 v 3.3 3.8 4.4 v vdet3 vdet3 detection voltage 3.0 v vdet3s hardware reset 2 hold voltage 2.0 v vdet3r hardware reset 2 release voltage 3.1 v symbol parameter measu rement condition standard unit min. typ. max. td(p-r) wait time to stabilize internal supply voltage when power-on vcc1 = 3.0 to 5.5 v 2 ms td(s-r) wait time to release hardwa re reset 2 vcc1 = vdet3r to 5.5 v 6 (1) 20 ms td(e-a) start-up time for vdet3 and vdet4 detection circuit vcc1 = 3.0 to 5.5 v 20 s td(p-r) vcc1 cpu clock recommended operating voltage td(p-r) wait time to stabilize internal supply voltage when power-on td(s-r) vcc1 cpu clock vdet3r td(s-r) wait time to release hardware reset 2 td(e-a) td(e-a) start-up time for vdet3 and vdet4 detection circuit vc26, vc27 vdet3 and vdet4 detection circuit stop operating vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 41 of 65 table 5.12 external clock input i = 0 to 4 i = 0 to 4 i = 0 to 4 i = 0 to 4 symbol parameter standard unit min. max. tc external clock input cycle time 31.25 ns tw(h) external clock input high (?h?) pulse width 13.75 ns tw(l) external clock input low (?l?) pulse width 13.75 ns tr external clock rise time 5 ns tf external clock fall time 5 ns table 5.13 timer a input (count source input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input high (?h?) pulse width 40 ns tw(tal) taiin input low (?l?) pulse width 40 ns table 5.14 timer a input (gate signal input in timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high (?h?) pulse width 200 ns tw(tal) taiin input low (?l?) pulse width 200 ns table 5.15 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns table 5.16 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns vcc1 = vcc2 = 5v timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) m32c/8a group rev.1.10 jul 15, 2007 page 42 of 65 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) i = 0 to 4 i = 0 to 4 i = 0 to 5 i = 0 to 5 i = 0 to 5 table 5.17 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high (?h?) pulse width 1000 ns tw(upl) taiout input low (?l?) pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns table 5.18 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 800 ns tsu(tain-taout) taiout input setup time 200 ns tsu(taout-tain) taiin input setup time 200 ns table 5.19 timer b input (count source input in event counter mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high (?h?) pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low (?l?) pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high (?h?) pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low (?l?) pulse width (counted on both edges) 80 ns table 5.20 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns table 5.21 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 43 of 65 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) i=0 to 4 i=0 to 5 table 5.22 a/d trigger input symbol parameter standard unit min. max. tc(ad) adtrg input cycle time (required for trigger) 1000 ns tw(adl) adtrg input low (?l?) pulse width 125 ns table 5.23 serial interface symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high (?h?) pulse width 100 ns tw(ckl) clki input low (?l?) pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi output hold time 0 ns tsu(d-c) rxdi input setup time 30 ns th(c-d) rxdi input hold time 90 ns table 5.24 external interrupt inti input (edge sensitive) symbol parameter standard unit min. max. tw(inh) inti input high (?h?) pulse width 250 ns tw(inl) inti input low (?l?) pulse width 250 ns vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 44 of 65 table 5.25 microprocessor mode note: 1. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. insert wait states or lower the operation frequency, f(bclk), if the calculated value is negative. symbol parameter standard unit min. max. tac1(rd-db) data input access time (rd standard) (note 1) ns tac1(ad-db) data input access time (ad standard, cs standard) (note 1) ns tac2(rd-db) data input access time (rd standar d, when accessing a space with the multiplexed bus) (note 1) ns tac2(ad-db) data input access time (ad standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(db-bclk) data input setup time 26 ns tsu(rdy-bclk) rdy input setup time 26 ns tsu(hold-bclk) hold input setup time 30 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns td(bclk-hlda) hlda output delay time 25 ns 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) + 1) tac1(rd-db) = 10 9 n f(bclk) - 35 [ns] (if external bus cycle is a + b , n = a + b) tac1(ad-db) = 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) - 1) tac2(rd-db) = 10 9 p f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , p = {(a + b - 1) 2} + 1) tac2(ad-db) = vcc1 = vcc2 = 5v timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) m32c/8a group rev.1.10 jul 15, 2007 page 45 of 65 switching characteristics (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.26 microprocessor mode (when accessing external memory space) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. 3. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (3) 0 ns th(wr-ad) address output hold time (wr standard) (3) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (3) 0 ns th(wr-cs) chip-select signal output hold time (wr standard) (3) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time -5 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (3) (note 1) ns tw(wr) wr output width (note 2) ns 10 9 f(bclk) 2 - 10 [ns] th(wr-db) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 n f(bclk) 2 - 15 [ns] (if external bus cycle is a + b , n = (b 2) - 1) tw(wr) = 10 9 m f(bclk) - 20 [ns] (if external bus cycle is a + b , m = b) td(db-wr) = vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 46 of 65 switching characteristics (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.27 microprocessor mode (when accessing external memory space with multiplexed bus) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 3. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 4. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 5. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (5) (note 1) ns th(wr-ad) address output hold time (wr standard) (5) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (5) (note 1) ns th(wr-cs) chip-select signal output hold time (wr standard) (5) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time -5 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (5) (note 1) ns td(bclk-ale) ale signal output delay time (bclk standard) 18 ns th(bclk-ale) ale signal output hold time (bclk standard) -2 ns td(ad-ale) ale signal output delay time (address standard) (note 3) ns th(ale-ad) ale signal output hold time (address standard) (note 4) ns tdz(rd-ad) address output float start time 8 ns 10 9 f(bclk) 2 - 10 [ns] th(rd-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(rd-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-db) = 10 9 m f(bclk) 2 - 25 [ns] (if external bus cycle is a + b , m = (b 2) - 1) td(db-wr) = 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a + b , n = a) td(ad-ale) = 10 9 n f(bclk) 2 - 10 [ns] (if external bus cycle is a + b , n = a) th(ale-ad) = vcc1 = vcc2 = 5v m32c/8a group rev.1.10 jul 15, 2007 page 47 of 65 figure 5.2 p0 to p15 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30 pf p11 p12 p13 p14 p15 note 1 note: 1. p11 to p15 are provided in the 144-pin package only. m32c/8a group rev.1.10 jul 15, 2007 page 48 of 65 figure 5.3 vcc1 = vcc2 = 5 v timing diagram (1) vcc1=vcc2=5v taiin input tc(ta) tw(tah) tw(tal) taiout input tc(up) tw(uph) tw(upl) taiout input (counter increment/ decrement select input) taiin input (count on falling edge) taiin input (count on rising edge) th(tin-up) tsu(up-tin) in event counter mode tbiin input tc(tb) tw(tbh) tw(tbl) adtrg input tc(ad) tw(adl) clki tc(ck) tw(ckh) tw(ckl) txdi th(c-q) td(c-q) rxdi tsu(d-c) th(c-d) inti input tw(inl) tw(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more ("l" width) xin input tc tw(l) tw(h) tr tf taiin input taiout input in event counter mode with two-phase pulse tc(ta) tsu(tain-taout) tsu(tain-taout) tsu(taout-tain) tsu(taout-tain) m32c/8a group rev.1.10 jul 15, 2007 page 49 of 65 figure 5.4 vcc1 = vcc2 = 5 v timing diagram (2) microprocessor mode bclk rd (separate bus) wr, wrl, wrh (separate bus) rd (multiplexed bus) wr, wrl, wrh (multiplexed bus) rdy input tsu(rdy-bclk) th(bclk-rdy) hi-z tsu(hold-bclk) td(bclk-hlda) bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 measurement conditions -vcc1 = vcc2 = 4.2 to 5.5 v -input high and low voltage: vih = 4.0 v, vil = 1.0 v -output high and low voltage: voh = 2.5 v, vol = 2.5 v vcc1=vcc2=5v th(bclk-hold) td(bclk-hlda) m32c/8a group rev.1.10 jul 15, 2007 page 50 of 65 figure 5.5 vcc1 = vcc2 = 5 v timing diagram (3) vcc1=vcc2=5v microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the mcu is used stand-alone. a maximum of 35 ns is guaranteed for td(bclk-ad) + tsu(db-bclk). 2. varies with operation frequency: tac1(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) + 1) tac1(ad-db) = (tcyc x n - 35) ns.max (if external bus cycle a + b , n = a + b) read timing (1 + 1 bus cycle) write timing (1 + 1 bus cycle) notes: 3. varies with operation frequency: t d(db-wr) = (tcyc x m - 20) ns.min (if external bus cycle a + b , m = b) t h(wr-db) = (tcyc / 2 - 10) ns.min t h(wr-ad) = (tcyc / 2 - 10) ns.min t h(wr-cs) = (tcyc / 2 - 10) ns.min t w(wr) = (tcyc / 2 x n - 15) ns.min (if external bus cycle a + b , n = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage: vih = 2.5 v, vil = 0.8 v - output high and low voltage: voh = 2.0 v, vol = 0.8 v tcyc= 10 9 f(bclk) bclk csi adi bhe dbi t h(bclk-cs) -3ns.min t d(bclk-cs) 18ns.max tcyc t d(bclk-ad) 18ns.max t h(wr-ad) (3) t h(bclk-wr) -5ns.min t d(db-wr) (3) th (bclk-ad) -3ns.min t d(bclk-wr) 18ns.max t w(wr) (3) t h(wr-db) (3) t h(wr-cs) (3) wr,wrl,wrh bclk csi adi bhe rd db t h(bclk-cs) -3ns.min t h(rd-cs) 0ns.min t d(bclk-cs) 18ns.max (1) tcyc t d(bclk-ad) 18ns.max (1) 18ns.max t d(bclk-rd) t h(rd-ad) 0ns.min t h(bclk-rd) -5ns.min t ac1(rd-db) (2) t ac1(ad-db) (2) hi-z t h(rd-db) 0ns.min t su(db-bclk) 26ns.min (1) th (bclk-ad) -3ns.min m32c/8a group rev.1.10 jul 15, 2007 page 51 of 65 figure 5.6 vcc1 = vcc2 = 5 v timing diagram (4) bclk csi adi bhe rd ale td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (1) th(ale-ad) (1) tdz(rd-ad) 8ns.max tac2(rd-db) (1) th(bclk-cs) -3ns.min th(rd-db) 0ns.min th(bclk-ad) -3ns.min td(bclk-ad) 18ns.max adi /dbi td(bclk-rd) 18ns.max tac2(ad-db) (1) th(bclk-rd) -5ns.min th(rd-ad) (1) tcyc address notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(rd-ad) = (tcyc / 2 - 10) ns.min, t h(rd-cs) = (tcyc / 2 - 10) ns.min t ac2(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) - 1) t ac2(ad-db) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b , p = {(a + b - 1) x 2} + 1) notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(wr-ad) = (tcyc / 2 - 10) ns.min, t h(wr-cs) = (tcyc / 2 - 10) ns.min t h(wr-db) = (tcyc / 2 - 10) ns.min t d(db-wr) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b , m = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage vih = 2.5 v, vil = 0.8 v - output high and low voltage voh = 2.0 v, vol = 0.8 v address vcc1=vcc2=5v microprocessor mode (when accessing an external memory space with the multiplexed bus) read timing (2 + 2 bus cycle) tcyc= 10 9 f(bclk) bclk csi adi bhe wr,wrl,wrh write timing (2 + 2 bus cycle) td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (2) th(ale-ad) (2) td(db-wr) (2) th(wr-cs) (2) td(bclk-ad) 18ns.max td(bclk-wr) 18ns.max th(bclk-wr) -5ns.min tcyc address data output th(wr-db) (2) adi /dbi ale address th(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min th(rd-cs) (1) data input tsu(db-bclk) 26ns.min th(wr-ad) (2) m32c/8a group rev.1.10 jul 15, 2007 page 52 of 65 table 5.28 electrical characteristics (1) (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 24 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter condition standard unit min. typ. max. voh output high ?h? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -1 ma vcc2 - 0.6 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) vcc1 - 0.6 vcc1 xout ioh = -0.1 ma 2.7 vcc1 v xcout high drive capability no load applied 2.5 v low drive capability no load applied 1.6 v vol output low ?l? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 1 ma 0.5 v xout iol = 0.1 ma 0.5 v xcout high drive capability no load applied 0v low drive capability no load applied 0v vt+ - vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int 5 , adtrg , cts0 to cts 4 , clk0 to clk4, ta0out to ta4out, nmi , ki0 to ki3 , rxd0 to rxd4, scl0 to scl4, sda0 to sda4 0.2 1.0 v reset 0.2 1.8 v vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 53 of 65 table 5.29 electrical characteristics (2) (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 24 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. table 5.30 electrical characte ristics (3) (vcc1 = vcc2 = 3.3 v, vss = 0 v, topr = 25 c) symbol parameter condition standard unit min. typ. max. iih input high ?h? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 3 v 4.0 a iil input low ?l? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 0v -4.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) vi=0v 40 70 500 k rfxin feedback resistance xin 3.0 m rfxcin feedback resistance xcin 20.0 m vram ram data retention voltage in stop mode 2.0 v symbol parameter condition standard unit min. typ. max. icc power supply current romless version f(cpu) = 24 mhz 22 33 ma f(cpu) = 16 mhz 15 ma f(cpu) = 8 mhz 9 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 1ma f(cpu) = 32 khz in low-power consumption mode 25 a f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 45 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 54 of 65 table 5.31 a/d conversion characteristics (vcc1 = vcc2 = avcc = vref = 3.0 to 3. 6 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 24mhz unless otherwise specified) notes: 1. the value when ad frequency is at 10 mhz. keep ad frequency at 10 mhz or less. if f(cpu) (=fad) is 24 mhz, divide f(cpu) by 3 to make it 8 mhz. the conversion time in this case is 6.1 s. 2. s&h not available. note: 1. measurement when one d/a converter is used, and the dai register (i = 0, 1) of the unused d/a converter is set to 00h. the current flown into the resistor ladder in th e a/d converter is excluded. ivref flows even if vcut bit in the ad0con1 register is set to 0 (vref not connected) symbol parameter measurement condition standard unit min. typ. max. ? resolution vref = vcc1 10 bits inl integral nonlinearity error (8-b it) vref = vcc1 = vcc2 = 3.3 v 2 lsb dnl differential nonlinearity error (8-bit) 1 lsb ? offset error (8-bit) 2 lsb ? gain error (8-bit) 2 lsb rladder resistor ladder vref = vcc1 8 40 k tconv 8-bit conversion time (1)(2) 4.9 s vref reference voltage 3 vcc1 v via analog input voltage 0 vref v table 5.32 d/a conversion characteristics (vcc1 = vcc2 = vref = 3.0 to 3.6 v, vss = avss = 0 v at topr = -20 to 85 c, f(cpu) = 24mhz unless otherwise specified) symbol parameter measurement condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % tsu setup time 3 s ro output resistance 4 10 20 k ivref reference power supply input current (note 1) 1.0 ma vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 55 of 65 timing requirements ( vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified ) i = 0 to 4 i = 0 to 4 i = 0 to 4 i = 0 to 4 table 5.33 external clock input symbol parameter standard unit min. max. tc external clock input cycle time 41 ns tw(h) external clock input high (?h?) pulse width 18 ns tw(l) external clock input low (?l?) pulse width 18 ns tr external clock rise time 5 ns tf external clock fall time 5 ns table 5.34 timer a input (count source input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input high (?h?) pulse width 40 ns tw(tal) taiin input low (?l?) pulse width 40 ns table 5.35 timer a input (gate signal input in timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high (?h?) pulse width 200 ns tw(tal) taiin input low (?l?) pulse width 200 ns table 5.36 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns table 5.37 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 56 of 65 timing requirements ( vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified ) i = 0 to 4 i = 0 to 4 i = 0 to 5 i = 0 to 5 i = 0 to 5 table 5.38 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high (?h?) pulse width 1000 ns tw(upl) taiout input low (?l?) pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns table 5.39 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 2 s tsu(tain-taout) taiout input setup time 500 ns tsu(taout-tain) taiin input setup time 500 ns table 5.40 timer b input (count source input in event counter mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high (?h?) pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low (?l?) pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high (?h?) pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low (?l?) pulse width (counted on both edges) 80 ns table 5.41 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns table 5.42 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 57 of 65 timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) i=0 to 4 i=0 to 5 table 5.43 a/d trigger input symbol parameter standard unit min. max. tc(ad) adtrg input cycle time (required for trigger) 1000 ns tw(adl) adtrg input low (?l?) pulse width 125 ns table 5.44 serial interface symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high (?h?) pulse width 100 ns tw(ckl) clki input low (?l?) pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi output hold time 0 ns tsu(d-c) rxdi input setup time 30 ns th(c-d) rxdi input hold time 90 ns table 5.45 external interrupt inti input (edge sensitive) symbol parameter standard unit min. max. tw(inh) inti input high (?h?) pulse width 250 ns tw(inl) inti input low (?l?) pulse width 250 ns vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 58 of 65 table 5.46 microprocessor mode note: 1. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. insert wait states or lower the operation frequency, f(bclk), if the calculated value is negative. symbol parameter standard unit min. max. tac1(rd-db) data input access time (rd standard) (note 1) ns tac1(ad-db) data input access time (ad standard, cs standard) (note 1) ns tac2(rd-db) data input access time (rd standar d, when accessing a space with the multiplexed bus) (note 1) ns tac2(ad-db) data input access time (ad standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(db-bclk) data input setup time 30 ns tsu(rdy-bclk) rdy input setup time 40 ns tsu(hold-bclk) hold input setup time 60 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns td(bclk-hlda) hlda output delay time 25 ns 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) + 1) tac1(rd-db) = 10 9 n f(bclk) - 35 [ns] (if external bus cycle is a + b , n = a + b) tac1(ad-db) = 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) - 1) tac2(rd-db) = 10 9 p f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , p = {(a + b - 1) 2} + 1) tac2(ad-db) = vcc1 = vcc2 = 3.3 v timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) m32c/8a group rev.1.10 jul 15, 2007 page 59 of 65 switching characteristics (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.47 microprocessor mode (when accessing external memory space) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. 3. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) 0 ns th(rd-ad) address output hold time (rd standard) (3) 0 ns th(wr-ad) address output hold time (wr standard) (3) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) 0 ns th(rd-cs) chip-select signal output hold time (rd standard) (3) 0 ns th(wr-cs) chip-select signal output hold time (wr standard) (3) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -3 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time 0 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (3) (note 1) ns tw(wr) wr output width (note 2) ns 10 9 f(bclk) 2 - 20 [ns] th(wr-db) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 n f(bclk) 2 - 15 [ns] (if external bus cycle is a + b , n = (b 2) - 1) tw(wr) = 10 9 m f(bclk) - 20 [ns] (if external bus cycle is a + b , m = b) td(db-wr) = vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 60 of 65 switching characteristics (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.48 microprocessor mode (when accessing external memory space with multiplexed bus) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 3. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 4. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 5. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) 0 ns th(rd-ad) address output hold time (rd standard) (5) (note 1) ns th(wr-ad) address output hold time (wr standard) (5) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) 0 ns th(rd-cs) chip-select signal output hold time (rd standard) (5) (note 1) ns th(wr-cs) chip-select signal output hold time (wr standard) (5) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -3 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time 0 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (5) (note 1) ns td(bclk-ale) ale signal output delay time (bclk standard) 18 ns th(bclk-ale) ale signal output hold time (bclk standard) -2 ns td(ad-ale) ale signal output delay time (address standard) (note 3) ns th(ale-ad) ale signal output hold time (address standard) (note 4) ns tdz(rd-ad) address output float start time 8 ns 10 9 f(bclk) 2 - 10 [ns] th(rd-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(rd-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 f(bclk) 2 - 20 [ns] th(wr-db) = 10 9 m f(bclk) 2 - 25 [ns] (if external bus cycle is a + b , m = (b 2) - 1) td(db-wr) = 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a + b , n = a) td(ad-ale) = 10 9 n f(bclk) 2 - 10 [ns] (if external bus cycle is a + b , n = a) th(ale-ad) = vcc1 = vcc2 = 3.3 v m32c/8a group rev.1.10 jul 15, 2007 page 61 of 65 figure 5.7 vcc1 = vcc2 = 3.3 v timing diagram (1) vcc1=vcc2=3.3v taiin input tc(ta) tw(tah) tw(tal) taiout input tc(up) tw(uph) tw(upl) taiout input (counter increment/ decrement select input) taiin input (count on falling edge) taiin input (count on rising edge) th(tin-up) tsu(up-tin) in event counter mode tbiin input tc(tb) tw(tbh) tw(tbl) adtrg input tc(ad) tw(adl) clki tc(ck) tw(ckh) tw(ckl) txdi th(c-q) td(c-q) rxdi tsu(d-c) th(c-d) inti input tw(inl) tw(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more ("l" width) xin input tc tw(l) tw(h) tr tf taiin input taiout input in event counter mode with two-phase pulse tc(ta) tsu(tain-taout) tsu(tain-taout) tsu(taout-tain) tsu(taout-tain) m32c/8a group rev.1.10 jul 15, 2007 page 62 of 65 figure 5.8 vcc1 = vcc2 = 3.3 v timing diagram (2) microprocessor mode bclk rd (separate bus) wr, wrl, wrh (separate bus) rd (multiplexed bus) wr, wrl, wrh (multiplexed bus) rdy input tsu(rdy-bclk) th(bclk-rdy) hi-z tsu(hold-bclk) td(bclk-hlda) bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 measurement conditions -vcc1 = vcc2 = 3.0 to 3.6 v -input high and low voltage: vih = 2.4 v, vil = 0.6 v -output high and low voltage: voh = 1.5 v, vol = 1.5 v vcc1=vcc2=3.3v th(bclk-hold) td(bclk-hlda) m32c/8a group rev.1.10 jul 15, 2007 page 63 of 65 figure 5.9 vcc1 = vcc2 = 3.3 v timing diagram (3) vcc1=vcc2=3.3v microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the mcu is used stand-alone. a maximum of 35 ns is guaranteed for td(bclk-ad) + tsu(db-bclk). 2. varies with operation frequency: tac1(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) + 1) tac1(ad-db) = (tcyc x n - 35) ns.max (if external bus cycle a + b , n = a + b) read timing (1 + 1 bus cycle) write timing (1 + 1 bus cycle) notes: 3. varies with operation frequency: t d(db-wr) = (tcyc x m - 20) ns.min (if external bus cycle a + b , m = b) t h(wr-db) = (tcyc / 2 - 20) ns.min t h(wr-ad) = (tcyc / 2 - 10) ns.min t h(wr-cs) = (tcyc / 2 - 10) ns.min t w(wr) = (tcyc / 2 x n - 15) ns.min (if external bus cycle a + b , n = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 3.0 to 3.6 v - input high and low voltage: vih = 1.5 v, vil = 0.5 v - output high and low voltage: voh = 1.5 v, vol = 1.5 v tcyc= 10 9 f(bclk) bclk csi adi bhe dbi t h(bclk-cs) 0ns.min t d(bclk-cs) 18ns.max tcyc t d(bclk-ad) 18ns.max t h(wr-ad) (3) t h(bclk-wr) 0ns.min t d(db-wr) (3) th (bclk-ad) 0ns.min t d(bclk-wr) 18ns.max t w(wr) (3) t h(wr-db) (3) t h(wr-cs) (3) wr,wrl,wrh bclk csi adi bhe rd db t h(bclk-cs) 0ns.min t h(rd-cs) 0ns.min t d(bclk-cs) 18ns.max (1) tcyc t d(bclk-ad) 18ns.max (1) 18ns.max t d(bclk-rd) t h(rd-ad) 0ns.min t h(bclk-rd) -3ns.min t ac1(rd-db) (2) t ac1(ad-db) (2) hi-z t h(rd-db) 0ns.min t su(db-bclk) 30ns.min (1) th (bclk-ad) 0ns.min m32c/8a group rev.1.10 jul 15, 2007 page 64 of 65 figure 5.10 vcc1 = vcc2 = 3.3 v timing diagram (4) bclk csi adi bhe rd ale td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (1) th(ale-ad) (1) tdz(rd-ad) 8ns.max tac2(rd-db) (1) th(bclk-cs) 0ns.min th(rd-db) 0ns.min th(bclk-ad) 0ns.min td(bclk-ad) 18ns.max adi /dbi td(bclk-rd) 18ns.max tac2(ad-db) (1) th(bclk-rd) -3ns.min th(rd-ad) (1) tcyc address notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(rd-ad) = (tcyc / 2 - 10) ns.min, t h(rd-cs) = (tcyc / 2 - 10) ns.min t ac2(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) - 1) t ac2(ad-db) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b , p = {(a + b - 1) x 2} + 1) notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(wr-ad) = (tcyc / 2 - 10) ns.min, t h(wr-cs) = (tcyc / 2 - 10) ns.min t h(wr-db) = (tcyc / 2 - 20) ns.min t d(db-wr) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b , m = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 3.0 to 3.6 v - input high and low voltage vih = 1.5 v, vil = 0.5 v - output high and low voltage voh = 1.5 v, vol = 1.5 v address vcc1=vcc2=3.3v microprocessor mode (when accessing an external memory space with the multiplexed bus) read timing (2 + 2 bus cycle) tcyc= 10 9 f(bclk) bclk csi adi bhe wr,wrl,wrh write timing (2 + 2 bus cycle) td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (2) th(ale-ad) (2) td(db-wr) (2) th(wr-cs) (2) td(bclk-ad) 18ns.max td(bclk-wr) 18ns.max th(bclk-wr) 0ns.min tcyc address data output th(wr-db) (2) adi /dbi ale address th(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min th(rd-cs) (1) data input tsu(db-bclk) 30ns.min th(wr-ad) (2) m32c/8a group rev.1.10 jul 15, 2007 page 65 of 65 appendix 1. package dimensions terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 20.1 20.0 19.9 d 20.1 20.0 19.9 e 1.4 a 2 22.2 22.0 21.8 22.2 22.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e a - 1 revision history m32c/8a group datasheet rev. date description page summary rev.1.00 apr 01, 2007 ? first edition issued rev.1.10 jul 15, 2007 6 - 144-pin package added - table ?product list? revised notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or 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